In personal computer systems (PCs), data continuously is transferred on buses between various master elements to various target elements. Such systems usually include a pair of buses, a primary bus and a secondary bus. The primary bus typically is used by the central processing unit (CPU) of the computer for transferring data to and receiving data from targets such as memories and the like connected to the bus. The secondary bus also has master and target elements connected to it, such as various disk drives and the like.
For some systems, demands made by particular masters or for particular types of information are given a priority over requests for data transfer from other sources; and an arbiter or arbitration circuit functions to grant use of the bus in accordance with the particular configuration of the arbiter control. Use of the bus in such a case typically is provided on a cycle-by-cycle basis to optimize the utilization of the bus and most effectively utilize the operating characteristics of the CPU. Interchange of data between master and targets on such a bus may be accomplished, either in a fixed request priority system or in a rotating priority mode, or in any desired priority mode determined to be the most effective for the system employed.
The performance of the secondary input/output (I/O) buses in PC systems is increasing. As a consequence, the method of data transfer between the primary bus and a secondary bus becomes more critical. Modern PC systems support multiple master elements on both the primary and secondary buses. As a consequence, a central arbitration mechanism or circuit is required for each bus. Data frequently is transferred between a master and a target on the same bus, either the primary bus or the secondary bus. When transfers of data occur between the two buses, however, currently two different arbitration methods are employed.
The first arbitration method, currently used for transferring data between primary and secondary buses in PC system, is known as "interlocked arbitration". Interlocked arbitration systems require that the secondary bus arbiter gains mastership of the primary bus by way of the primary bus arbiter prior to granting use of the secondary bus to one of its master elements. When this system is used, it favors secondary-to-primary transfer cycles, saving time in one of two ways. Interlocked arbitration ensures that the primary bus is available if the transfer is a secondary-to-primary transfer, rather than a secondary-to-secondary transfer. In addition, interlocked arbitration ensures that the secondary bus is available if the primary transfer is a primary-to-secondary transfer. This prevents the need to consume time resolving deadlock conditions which arise if a primary-to-secondary and secondary-to-primary cycle were to be permitted to occur simultaneously.
In an interlocked system, time also is saved, once the bus is acquired, since primary bus mastership is maintained by any secondary master request through multiple secondary-to-primary cycles, thus eliminating primary bus arbitration between every cycle. Since most PC peripheral data is transferred in large blocks over many cycles, the time saved through the elimination of primary bus arbitration between every cycle can be significant. This time saving for secondary-to-primary cycles, however, is realized at a cost to primary bus bandwidth for two reasons. The interlocked arbitration system and method holds the primary bus mastership, even for secondary-to-secondary transfers. Clearly, secondary-to-secondary transfers do not involve the primary bus; and holding the primary bus for such transfers deprives use of the primary bus for any primary-to-primary transfers which may be requested during this time. In addition, primary bus mastership is held while communication with the secondary master occurs to begin the cycle.
A second method of arbitration used to control data transfer between primary and secondary buses is called concurrent arbitration. Concurrent arbitration operates the primary bus arbiter and the secondary bus arbiter independently. As a result, concurrent arbitration favors primary bus bandwidth by saving primary bus cycles in two ways. Unlike interlocked arbitration systems, the secondary arbiter in a concurrent arbitration system does not attempt to gain mastership of the primary bus prior to granting secondary mastership to one of its requesting elements. Primary bus mastership only is requested after the secondary master cycle has begun and the address identifies a target element on the primary bus. This eliminates holding of the primary bus during secondary-to-secondary transfers. In addition, the primary bus is not held during communication between the secondary arbiter and its requesting master to begin the master cycle. The disadvantage of this system, however, is that the increased primary bus bandwidth comes at a cost to secondary-to-primary transfer performance, since primary bus arbitration is required between each and every secondary master cycle. This is contrasted with interlocked arbitration, where multiple cycles are maintained for transferring large blocks of data. In addition, concurrent arbitration deadlock conditions can occur when a primary-to-secondary cycle and a secondary-to-primary cycle are pending simultaneously. In such cases, one of the cycles, in accordance with a preset deadlock operating sequence, must be backed off for a subsequent retry. This consumes time, which degrades the performance characteristics of the computer.
Accordingly, it is desirable to provide an arbitration system and method which overcomes the disadvantages of the prior art mentioned above, and which optimizes the advantages of both interlocked arbitration and concurrent arbitration systems.